The present invention generally relates to computer-assisted design of electronic circuits, and more particularly to automating timing-driven optimizations in various phases of implementing a circuit design.
The place and route phases of implementing a circuit design generally involve generating a layout of the circuit elements on a chip and defining the signal lines that connect the elements. To satisfy various physical design requirements, the circuit layout is typically optimized based on physical resources. For example, optimization of the layout can be based on resources such as area and wire length. That is, it is desirable for the circuit to occupy the smallest area possible and the smallest possible total wire length.
Performance requirements for a circuit are also considered during the place and route phases. The required performance of a circuit is typically specified by a user and is expressed as the required frequency. This requirement translates to a maximum allowable delay for paths between boundary elements, for example, flip-flops. The maximum path delay that is acceptable is a timing constraint parameter that is provided to the place and route processes.
When place-and-route is performed without regard for timing constraints, a valid placed and routed design can be generated relatively quickly. However, since timing constraints are not considered, the result may not satisfy the performance requirements. When timing constraints are introduced to the place-and-route processes, the placer and router perform delay-driven optimization, which requires a much longer runtime.
In conjunction with the long runtimes associated with delay-driven optimization, the process of maximizing the performance of a circuit may be an iterative process. That is, a designer may choose an initial timing constraint, run the placer and router, and if the design was successfully placed and routed, repeat the process using a tighter timing constraint. However, the next iteration of the process using the new timing constraint may not be feasible, thereby wasting a considerable amount of time in rerunning the placer and router. Alternatively, placing and routing under the new timing constraint may leave room for even further improvement in the performance, thereby requiring another iteration of the process with a further tightened timing constraint. It can be seen that creating a placed and routed design with optimal performance can be a time-consuming process.
A method and apparatus that address the aforementioned and related problems in the place-and-route phases of implementing a circuit design, as well as in other phases of implementation, are therefore desirable.
In various embodiments, a method and apparatus are provided for automatic, timing-driven optimization in various phases of implementing a circuit design. The timing constraint that is applied during different phases of implementation is dynamically varied in order to improve circuit performance. The processes and apparatus allow automation of the task of determining a circuit""s maximum performance. In general, the process begins by determining the timing performance of a given layout. The process then automatically determines a new, tighter timing constraint. In one embodiment, a selected portion of the connections becomes critical in choosing the new, tighter timing constraint. The new timing constraint is then applied in producing a new layout. Slack values associated with paths in the placed/routed design are used in deriving the new timing constraint from the selected number of critical connections.
It is observed that the level of difficulty associated with a timing constrained place-and-route is proportional to the number of connections in a design that are critical. Making a connection xe2x80x9ccriticalxe2x80x9d refers to setting a new timing constraint such that the delay of at least one path passing through the connection is greater than the time associated with the timing constraint. To automatically adjust the timing constraint, a selected number of the connections are deemed to be critical. That is, a new timing constraint is chosen such that signal paths through the desired number of connections will become critical in the next iteration of placing or routing the design. By gradually and automatically tightening the timing constraint as a function of a number of critical connections, in the place-and-route phase as well as in other phases of the implementation, a designer""s time as well as computation time can be saved.
Various other embodiments are set forth in the Detailed Description and claims which follow.